ZISC@

» 4stack Processor    Research project for high performance, low cost computing. Uses stack-based instructions for a 4-way VLIW processor. Implemented in current technology, it would outrun high-end DSPs (TMS 320C6x, TigerSHARC), and let the full program run on one processor,    http://www.jwdt.com/~paysan/4stack.html

» A No Instruction Set Processor    Benefits: simple, easily pipelined, useful in self-clocked systems, very flexible and optimizable, good memory access, highly. Problems: awkward to program. [cowlark.com]    http://www.cowlark.com/nisc.html

» E25 Computer Architecture: Lab 5: OISC: One Instruction Set Computer    Class project to design and implement One Instruction Set Computer; using instruction: SUBLEQ A B C. Meaning: subtract value in M(A) from M(B) and store it in M(B), if result is not positive, go to instruction C. Descriptions, diagrams, code, tables.    http://www.sccs.swarthmore.edu/users/06/adem/engin/e25/finale/

» Enumera, Inc.    Goal: dominate very low cost, low power, single core CPU market, and have the only ultra-high-end supercomputer on-a-chip system. Because the CPU core is so small, it is possible to put 1000s of cores and memory in one IC chip package.    http://www.enumera.com/

» Forth Chips    References, links to Forth and stack machines in various technologies.    http://www.ultratechnology.com/chips.htm

» Java Optimized Processor    JOP is the implementation of a small java processor with the JVM fitting in a FPGA.    http://www.jopdesign.com/

» MOVE Project    Automatic Synthesis of Application Specific Processors. Goal: design, build high-performance processors via a new class of transport-triggered architectures, TTAs, programmed by specifying data-transports not operations; well suited for application specif    http://ce-serv.et.tudelft.nl/MOVE/

» MSL16 Processor    Minimal instruction set, small, low power 16-bit CPU optimized to run Forth on a Xilinx FPGA. When system is stable, VHDL source code for CPU and all other code will be released to make a full open source public domain CPU.    http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/old/msl16/msl16.html

» Microprocessor Architectures from VLIW to TTA    By Henk Corporaal; John Wiley, 1998, ISBN 047197157X. Introduces Transport Triggered Architectures, TTAs. In standard architectures, programmed operations trigger internal data transports. TTAs work by programming data transports themselves. This removes    http://www.ics.ele.tue.nl/~heco/documents/TTAbook/TTAbook.html

» Minimal Instruction Set Computers    Stack-based processors, 5-bit words, 25 instructions, 7000 transistors, 80 MIPS, 50 milliwatts, low cost; designed by Chuck Moore, creator of Forth programming language.    http://www.ultratechnology.com/misc.html

» NASA: Space Related Applications of Forth    Uses of Forth microprocessors and programming language: controllers for spacecraft flight systems, on-board payload experiments, ground support; hardware or software to build or test flight or ground systems.    http://forth.gsfc.nasa.gov/

» New Micros, Inc.    Designs, builds: single board computers (SBC), peripherals, embedded systems, PCB design/layout, high level programming (industry leaders in Forth), custom design work; large line of stock products: from full handheld computers to development packages. Si    http://www.newmicros.com/

» PTSC: Patriot Scientific Corp.    Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies.    http://www.ptsc.com/

» SUBLEQ    Simple one instruction language; type of OISC; specifications from Clive Gifford eigenratios self-interpreter page. Each subleq instruction has 3 operands which are memory addresses. Oleg Mazonka.    http://mozaika.com.au/oleg/subleq/

» SandPiper Technology    Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible.    http://www.sandpipers.com/

» Stack Computers & Forth    Philip J. Koopman, Jr., CMU page. Reports, studies, and links. Compares: CISC, RISC, Stack systems; 2 and 3 stack systems.    http://www.ece.cmu.edu/~koopman/stack.html

» Stack Computers: The New Wave    By Philip J. Koopman, Jr; Ellis Horwood, 1989, ISBN 0470214678. Read on-line, or download in formats: HTML, PDF, zip file. First book to explore a new breed of stack computers led by introduction of Novix NC4016. [Free]    http://www.ece.cmu.edu/~koopman/stack_computers/

» T-Recursive Technology    Embedded systems consultant for small (8/16-bit) and distributed microprocessor systems. Contract hardware and software development for most microcontrollers. Specialist: Forth, Assembly, C. By Bradford J. Rodriguez, Ph.D.    http://www.zetetics.com/recursiv/capabil.htm#Hardware

» The Ultimate RISC    Explains extreme, simple RISC, with only one instruction, move memory to memory; yet it is useful. Revision of paper first published in ACM Computer Architecture News.    http://www.cs.uiowa.edu/~jones/arch/risc/

» Triangle Digital Services Ltd.    Small, powerful Forth embedded computers: let you quickly design applications: controls, portable instruments, terminals, data loggers, GPS, CAN bus, multitasking, LCD and keyboard systems. High level language makes development simple and fast; needs no P    http://www.triangledigital.com/

» Wikipedia: One Instruction Set Computer    Online encyclopedia article about this single machine language opcode, with links to related articles.    http://en.wikipedia.org/wiki/One_instruction_set_computer

» Wikipedia: Transport Triggered Architectures    Online encyclopedia article about this approach to computer architecture.    http://en.wikipedia.org/wiki/Transport_Triggered_Architectures

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